#--  Synopsys, Inc.
#--  Version I-2014.03LC 
#--  Project file C:\isplever_classic2_0\examples\tlc_engine_v1b\run_options.txt

#project files
add_file -vhdl -lib work "./tlc_engine.vhd"



#implementation: "tlc_engine_v1b"
impl -add tlc_engine_v1b -type fpga

#
#implementation attributes

set_option -num_critical_paths 3
set_option -num_startend_points 0

#device options
set_option -technology ispmach4000b
set_option -part LC4064B
set_option -package T44C
set_option -speed_grade -2.5
set_option -part_companion ""

#compilation/mapping options
set_option -top_module "tlc_engine"

# mapper_options
set_option -frequency 200
set_option -auto_constrain_io 1
set_option -default_enum_encoding default
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# Lattice ispMACH4000
set_option -maxfanin 20
set_option -RWCheckOnRam 1
set_option -maxterms 16
set_option -areadelay 0
set_option -disable_io_insertion 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 1
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./tlc_engine.edi"

#set log file 
set_option log_file "C:/isplever_classic2_0/examples/tlc_engine_v1b/tlc_engine.srf" 
impl -active "tlc_engine_v1b"
